| 摘要 |
PURPOSE:To provide a bit pattern detection circuit in which initial synchronization is established quickly and-locking is executed even when synchronization is stepped-out and to provide a PN pattern detection circuit capable of detecting the input of a PN pattern continuously. CONSTITUTION:A PN pattern detection circuit 12 provides the output of received PN pattern data as they are to suppress an error bit output from a data comparator circuit 14 and allows a synchronization discrimination circuit 16 to decide establishment of synchronization and the circuit 16 brings the PN pattern generating circuit 12 to the internal generating state. When lots of error bits are generated by the detection of the data at a PN pattern detection circuit 15, re-locking is executed as out of synchronism. The PN pattern detection circuit 15 processes the inputted bit pattern. The PN pattern is not detected only when lots of unmatching cases take place within a predetermined period based on the output of a built-in decoder having the similar internal configuration to that of the PN pattern detection circuit 12. |
