| 摘要 |
<p>PURPOSE:To reduce the number of waste cells while suppressing the increase of a hardware scale by varying the through-put of an input port in proportion to the number of arriving cells. CONSTITUTION:Two cells are flowing into an input port 11 per a unit time, and one cell is flowing into input ports 12 and 14 per the unit time. Each cell is outputted to output ports 61-64 nearest to the input ports 11-14. The number of the cells per the unit time stored on an input buffer 21 of the input port 11 is 2, and a switch control circuit 5 instructs a DMUX circuit 31 of the port 11 that the number of cell separation is 2 by a control part 81. The circuit 31 successively distributes the input cells to inside buffers 311 and 312 according to the instructed number of separation. The number of cell separation of buffers 22 and 23 is 1, and the input cells are distributed to buffers 321 and 341. The circuit 5 monitors the buffers 311-342 so as to be in a state that the cells are stored, outputs switch control information 10, and transmits it to the ports 61-64. Thus, the number of the waste cells can be reduced by variably controlling the through-put of the port 11 at which the number of input loads is large.</p> |
