| 摘要 |
<p>A frequency synthesizer, which realizes speed-up of channel switching between channels having separated frequencies, has an EEPROM (10) which stores the phase difference between a first frequency divider (2) and a second frequency divider (4) producing outputs corresponding to the frequencies of the channels to be switched. A delay circuit (7) delays the output of the second frequency phase divider by an amount corresponding to an amount of the phase difference stored in the EEPROM. A controller (9) supplies the outputs of the second frequency divider and the delay circuit to a phase detector (5). Further, the controller stops a PLL operation and restarts it in synchronism with a leading edge of, preferably, a second period of the output signal of the reference oscillator to which the preset phase difference is given. <IMAGE></p> |
