| 摘要 |
PURPOSE:To make equal the output impedance of the original signal and the delay signal, by forming the 1 horizontal period delay circuit consisting of charge transfer element and the branch circuit having almost the same output resistance connected to the input side of the circuit, on the one semiconductor substrate. CONSTITUTION:On the semiconductor substrate, the CCD delay circuit 11 being one horizontal period delay circuit and the inversion branch circuit 12 consisting of the MOS transistor Tr are unifiedly integrated. The transfer clocks phi1 to phi4 are fed to the terminals 11 to 25 of the circuit 11 to give delay by 1 H, the output is fed to MOSTr 29, and the output is made at the terminal V1 with sampling of pulse phi2 by Tr 29 and 30. The input signal fed to the gate input terminal I of the circuit 12 is fed to Tr 36 and 37 constituting the source follower, and the output resampled with Tr 35 and 38 is outputted at the terminal V2. Further, the output resistance of the circuits 11 and 12 is approximately made equal, and the output of the terminals V1 and V2 is added or subtracted at the subtraction circuit 13 into output. |
