发明名称 HIGH SPEED ARITHMETIC UNIT
摘要 PURPOSE:To simultaneously execute an arithmetic operation including the arithmetic operator of more than two on a high speed arithmetic unit in a processor in a computer system. CONSTITUTION:Registers 21, 22, 22,..., and 2n temporarily hold numerical data D1, D2,..., and Dm constituting bit data of four bits and the like, for example, received from a storage means 10. An allocation means 30 allocates bit data BD for respective pieces of numerical data D1, D2,..., and D, outputted from the registers 21, 22,... and 2n. An addition means 40 executes addition at every bit data BD allocated to the allocation means 30, and outputs an arithmetic result AD.
申请公布号 JPH06274318(A) 申请公布日期 1994.09.30
申请号 JP19930058168 申请日期 1993.03.18
申请人 FUJITSU LTD 发明人 SAWADA HIDEHO;MINODA YORIKO;TAKIZAWA YUKA;MARUYAMA FUMIHIRO
分类号 G06F7/38;G06F7/508;G06F7/52;G06F7/527;G06F7/53;G06F7/533 主分类号 G06F7/38
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