发明名称 INVERTER CIRCUIT
摘要 PURPOSE:To provide an inverter circuit, in which an output ripple is reduced effectively. CONSTITUTION:An inverter circuit includes a pair of PWM inverters that generate each output with opposite polarity, and the outputs from a plurality of inverter blocks 1 to 4, in which the inverters have different carrier wave phases, are connected in series or parallel. A synthetic signal of the outputs from the inverter blocks 1 to 4 is generated, and thereby a ripple factor is sharply reduced.
申请公布号 JPH06276678(A) 申请公布日期 1994.09.30
申请号 JP19930085618 申请日期 1993.03.18
申请人 N F KAIRO SEKKEI BLOCK:KK 发明人 ARAKI KUNIYA;ABE BUNGO;WATANABE TAKEYOSHI
分类号 H02J1/02 主分类号 H02J1/02
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