| 摘要 |
PURPOSE:To accelerate the address decoding of a RAM with the large scale number of words by constituting a row address decoding circuit with a first logic gate group and a second logic gate group, and making a part of the first logic gate group in common between plural pieces of adjacent row addresses. CONSTITUTION:The decoding circuit decoding the binary row addresses A0-A7, etc., of eight bits is constituted of the first logic gate group and the second logic gate group dividing an address signal to plural parts and decoding them. The first logic gate group is formed by a logic gate group alpha decoding low-order address bit group A0-A3 incorporating the least significant address bit A0 and the logic gate group beta decoding high-order and middle-order address bits A4-A7 group. Then, the gate group beta is shared for plural pieces of rows of adjacent two pieces, etc., and a free area for the passing wiring of high-order address is enlarged, and the address decoding time is accelerated in the RAM with the large scale number of words. |
