发明名称 MULTIPLICATION CIRCUIT
摘要 PURPOSE:To provide the multiplication circuit which suppresses the number of steps longitudinally piling transistors at a minimum and is convenient for voltage reduction. CONSTITUTION:While using 1st-4th basic circuits U1-U4, terminals A of the 1st and 3rd basic circuits U1 and U3 are connected to a 1st terminal 1, the terminals A of the 2nd and 4th basic circuits U2 and U4 are connected to a 2nd terminal 2, terminals b of the 1st and 4th basic circuits U1 and U4 are connected to a 3rd terminal 3, and the terminals B of the 2nd and 3rd basic circuits U2 and U3 are connected to a 4th terminal 4 respectively. Then, terminals C of the 1st and 2nd basic circuits U1 and U2 are connected in common, and the terminals C of the 3rd and 4th basic circuits U3 and U4 are connected in common.
申请公布号 JPH06274659(A) 申请公布日期 1994.09.30
申请号 JP19930081063 申请日期 1993.03.17
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 ONODERA KIYOMITSU
分类号 G06G7/163;(IPC1-7):G06G7/163 主分类号 G06G7/163
代理机构 代理人
主权项
地址