| 摘要 |
PURPOSE:To enable efficient data processing by reducing the load of a CPU at a third bus when connecting a first bus and a second bus to the third bus. CONSTITUTION:A text bus (first bus) 41 and a graphic bus (second bus) 42 are connected through a connector 61 to a system bus (third bus) 11. When the third bus 11 sends an address for accessing a memory connected to the first and second buses 41 and 42, correspondent addresses are translated by address translation tables 85 and 86 for text bus and graphic bus and sent to the first and second buses 41 and 42 and data signal 71D and 79D read from the result are latched by text and graphic latch circuits 105 and 108, when calculated by a computing element 97 and sent to the third bus 11 as a data signal 78D. The CPU connected to the third bus 11 becomes free from operation processing or the like. |
