发明名称 DETERMINATION OF OPTIMAL CLOCK SIGNAL FOR SAMPLING A PACKET
摘要 An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.
申请公布号 WO9422248(A1) 申请公布日期 1994.09.29
申请号 WO1994US02622 申请日期 1994.03.11
申请人 APPLE COMPUTER, INC. 发明人 VAN BRUNT, ROGER;HILLMAN, DANIEL, L.;NILSON, CHRISTOPHER;OPRESCU, FLORIN;TEENER, MICHAEL, D.
分类号 H04L7/00;H04L7/02;H04L7/033;H04L7/04;H04L7/10;(IPC1-7):H04L7/033 主分类号 H04L7/00
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