| 摘要 |
<p>A differential-to-CMOS level signal converter which receives a first differential signal having a small amplitude difference between the binary signals. The differential-to-CMOS level converter amplifies and level shifts the binary differential signal and outputs a single-ended CMOS level signal suitable for use by digital CMOS logic. A circuit (E) for biasing the differential-to-CMOS level converter is coupled to the level shifting circuitry (C).</p> |
