发明名称 INTELLIGENT MEMORY ARCHITECTURE
摘要 <p>An Intelligent Memory device comprises a data module, an Access Module and an Interface Module and is configured to allow data manipulation to take place within the Data Module without the involvement of the host system. The Memory Module consists of a plurality of Data Storage elements (DS) each of which has an associated Three Port Switch (3S) enabling data communication between the Data Storage elements (DS) without data having to tie up the data bus of the host system. The Access Module comprises a 1:N switch (1S) and Range Decoder (RD). The 1:N switch provides access between the Host system data bus and the Three Port switches (3S) of the Data Module, while the Range Decoder (RD) decodes a range of addresses to be affected by an internal memory operation. The Interface Module comprises an Instruction Decoder (ID) and Control Logic (CL) and is responsive to an instruction sent to the Intelligent Memory Device by the Host system to control the operation of internal memory manipulations. Intelligent Memory devices can be used to perform a variety of memory data manipulations of varying complexity, including summing, gating, searching and shifting. In the simplest form of Intelligent Memory device only two operations are provided, these being a shift up and a shift down, each of which causes the data in a range of contiguous memory locations to be shifted by one memory location in the given direction.</p>
申请公布号 WO1994022090(A1) 申请公布日期 1994.09.29
申请号 AU1994000145 申请日期 1994.03.23
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