CIRCUIT FOR CONTROLLING BIT LINE DIVISION OF DRAM CELL ARRAY

摘要

The circuit comprises several cell blocks which are composed of DRAM cell array, several bitlines which are connected to several cells of the cell block, a precharge circuit and a sense amplifier which are connected to the bitline separation switching block, and a column selection switching block which transports the output signal of the sense amplifier to databus line. The bitline switching block of the bitline control circuit is composed of the first switching element for separating a pair of bitline by the bitline selection signal and the second switching element for separating the other bitlines.