| 摘要 |
PURPOSE:To extend the degree of freedom of the timing design of transmission to easily attain high-speed in serial communication by selecting the output timing of transmission data from either of the rise or fall of a transmission clock by specification from outside. CONSTITUTION:Transmission data is outputted from a TXD terminal by way of a shift register from a transmitter. The transmitter and the shift register operate in synchronizing with the rise of an internal transmission clock TXCI. TXC 1 is generated by making a transmission clock TXC inputted from a TXC terminal to pass through an EX-OR circuit. Either input of the EX-OR circuit is connected to an external switch SWT to be '1' when SWT is upper and to be '0' when SWT is lower. TXCI is the inversion of TXC when SWT is upper and it is the same as TXC when SWT is lower. Thus, as the changing timing and the sampling timing of data can freely be set by specification from outside, high-speed can easily be attained. |
