发明名称 INFORMATION PROCESSOR PROVIDED WITH MAIN STORAGE CONTROLLER HAVING ERROR CORRECTION/DETECTION FUNCTION
摘要 PURPOSE:To speed up main storage write access in a size which does not come to the generation unit of an error correction code by means of a main storage controller. CONSTITUTION:A main storage 3 managed by setting system bus width to be one sub-block and N-pieces of the sub-blocks to be one block is constituted of sub-main storages 30-0 to 30-(N-1) corresponding to N-pieces of the sub-blocks. A cache memory 41 is provided in the main storage controller 4 generating the correction code with system bus width as the unit. The main storage controller 4 rewrites only a data part in the requested sub-block among data into request data, extends it to system bus width, generates the correction code based on the extended data and writes it into the corresponding sub-storage in the main storage 3 if block data of a request destination is registered in the cache memory 41 when write access is the size which does not come to system bus width.
申请公布号 JPH06266618(A) 申请公布日期 1994.09.22
申请号 JP19930057347 申请日期 1993.03.17
申请人 TOSHIBA CORP 发明人 SATO YOSHIYUKI
分类号 G06F11/10;G06F12/08 主分类号 G06F11/10
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