PREPARATION OF METHOD OF RESISTING AND EVENING IT SILYLATION AND INTEGRATED CIRCUIT DEVICE

摘要

PURPOSE: To provide a multilayered semiconductor manufacturing process of high precision by using a simplified method, and simplify the well-known three- layer working technique without damaging resolution of process. CONSTITUTION: A process wherein a topograph on a substrate is covered with a flattening resist layer 52, a process wherein the flattening resist layer 52 is soft-baked in vapor or liquid in which silicon is contained, a process wherein a flattening layer is covered with an imaging resist layer 57, a process wherein the imaging resist layer 57 is soft-baked, a process wherein the imaging resist layer 57 is developed, and a process wherein the flattening layer is etched are contained. The flattening layer contains novolak and other organic polymer which are conventionally used in a lithography process. Especially, the polymer is selected from a group composed of novolak, poly methylmethacrylate, polydimethylglutaric imide and polyhydroxy styrene. The flattening layer contains organic acid moiety having compatibility with solvent used for dissolving resin. Especially, indole-3-carboxylic acid is used as acid moiety.