| 摘要 |
A row decoder for a semiconductor memory device is disclosed which includes a plurality of decoding circuits each driving a corresponding one of word lines in response to first and second control signals associated therewith. Each of the decoding circuits includes a first node supplied with the first control signal, a second node supplied with the second control signal, a first transistor connected between the first node and the corresponding word line and turned ON when the second control signal takes an active level, and a second transistor connected between the corresponding word line and a reference potential terminal and turned ON when the second control signal takes an inactive level. <IMAGE> |
