| 摘要 |
Input data symbols are written in a write buffer then to a sync adder, which appends a pseudo randomly (PN) generated sync bit to the MSB position of a four-symbol sync word data field, to generate a sync word. Sync words may or may not be randomized and sent to a receiver whereafter synchronization is recovered and perhaps de-randomized symbols are written into particular positions of an ECC block in a read buffer which are derivable from the PN sequence. The ECC block is a data array having multi-bit sync words making up its rows and the bit positions of the sync words making up its columns. Synchronization recovery apparatus conceptually looks at each bit position across a row and in a top-to-bottom direction down each of the columns to locate that column which contains the appended PN sequence. Sync recovery involves the receiver re-generating the same PN sequence that was generated at the transmitter. When the sync bit position is found, the data stream is assembled into fixed length sync words and written into the read buffer. Further, the position of the sync bit in the PN sequence is used to generate an address for writing the ECC codeword in a read buffer. Synchronization recovery circuit passes along to the read buffer both ECC codeword data symbols and sync bit position in the form of a read buffer address. Error rate measurement can be done by comparing a received PN sequence with a reconstructed PN sequence.
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