发明名称 EEPROM WRITE CONTROL SYSTEM
摘要 <p>PURPOSE:To shorten time required for writing by repeating checking when the writing of data for each bank is completed and writing in the bank again in the case of abnormality. CONSTITUTION:When a cycle to write in a bank 1 is executed, a signal 8 is outputted and reported during the write-in by the EEPROM of the bank 1. At the time of completion of writing up to a bank 4, all EEPROMs are in the process of writing, and therefore MPU1 is in the state of waiting for the completion of writing. When the writing signal is depleted, the completed bank number is reported to an address decode/address control circuit 16 by a response circuit 17, and a data check is started. Data from the bank 1 and the check code are reread, and a data check is performed. If 1 bit error is detected, it is reported to the circuit 16, and simultaneously, the corrected data are outputted on a data bus. The check is further repeated, and if abnormality is detected, rewriting is performed by the circuit 16; consequently, the time required for writing is shortened.</p>
申请公布号 JPH06259974(A) 申请公布日期 1994.09.16
申请号 JP19930049010 申请日期 1993.03.10
申请人 HITACHI LTD;HITACHI INSTR ENG CO LTD 发明人 SHIBUKAWA SHIGERU;ECHIGO NOBUYUKI
分类号 G06F12/06;G06F12/00;G11C16/02;G11C16/06;G11C17/00;(IPC1-7):G11C16/06 主分类号 G06F12/06
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