发明名称 PROCESSOR ELEMENT AND PARALLEL PROCESSING SYSTEM
摘要 PURPOSE:To efficiently perform a random communication through small hardware quantity without falling in a deadlock. CONSTITUTION:The processor element 16A has a memory 10 which has a normal area 12 and an intermediate data save area 11, and a communication device 1A. The communication device 1A has a port 2e connected to the memory 10, ports 2a and 2d leading outside the processor element 16A, and buffers 4a, 4d, and 4e. For example, the communication device 1A sends data out to the intermediate data save area 11 of the memory 10 from the buffer 4a through the port 2e, for instance, when a state wherein the data can not be sent outside the processor element from the buffer 4a through the port 2d continues for longer than a prescribed period of time. Thus, data are sent out of the buffer 4a, 4d, and 4e within a finite period of time without fail.
申请公布号 JPH06259396(A) 申请公布日期 1994.09.16
申请号 JP19930040789 申请日期 1993.03.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKABAYASHI ICHIRO
分类号 G06F15/16;G06F15/177;G06F15/80 主分类号 G06F15/16
代理机构 代理人
主权项
地址