TEST SIMPLIFICATION LOGIC SYNTHESIS SYSTEM AND TEST SIMPLIFYING CIRCUIT,申请号JP19930043077-传众专利搜索

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发明名称	TEST SIMPLIFICATION LOGIC SYNTHESIS SYSTEM AND TEST SIMPLIFYING CIRCUIT
摘要
申请公布号	JPH06259500(A)	申请公布日期	1994.09.16
申请号	JP19930043077	申请日期	1993.03.04
申请人	FUJITSU LTD	发明人	NAKADA TSUNEO
分类号	G01R31/28;G06F17/50;(IPC1-7):G06F15/60	主分类号	G01R31/28
代理机构		代理人
主权项
地址

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