| 摘要 |
PURPOSE:To facilitate high circuit integration of a basic function by realizing clock generation required for a terminal equipment connected to an ISDN basic interface with a digital circuit. CONSTITUTION:Clocks generated by a 1st frequency division circuit 1 are made into two clocks A, B with a different phase and a phase of a phase correction clock is corrected by selecting any of them. Furthermore, clocks by a 2nd frequency division circuit 2 are made into three clocks C, D, E with a different phase and the phase of an object clock generated by a 3rd frequency divider circuit 9 is corrected by selecting any of them. A prescribed relation is provided to the clocks A, B, C, D, E to make the corrected phase identical to each other, then the phase correction is controlled in common. A phase lag/phase lead signal generated by comparing the phase correction clock with a timing signal of a network clock to control the switching of the clocks A, B, C, D, E and the object clock in frequency synchronization with the network is obtained through digital circuit configuration. |
