| 摘要 |
PURPOSE:To easily and speedily specifies whether a parity error occurs to a parity error inspecting mechanism or memory. CONSTITUTION:This parity error inspecting mechanism consists of a central processing unit(CPU) 101 which outputs inspection data and control data to the memory, the memory 104 which stores parity data generated from the inspection data, a parity generator checker(PGC) 102 which generates the parity data to be stored in the memory 104, and inspects a pity error in read data and generates an error interruption signal (g), a parity register 103 which stores write/read data of the memory 104 and inspects the CPU 101, PCG 102, and memory 104, a check data transmission part A which generates a control signal (f) on the basis of the control data, and a control part B which inverts the read data on the basis of the control signal (f) and sends the data to the PGC 102 to make the CPU 101 check the PGC itself. |
