| 摘要 |
<p>A memory system utilizes a variable number of separately replaceable memory banks (65) which can be implemented with memory elements (73), such as dynamic random access memory (DRAM) chips, which are of differing speeds and/or sizes. A programmable address decoder (91) contains a writable memory (95) and is controlled by a diagnostic interface (96) coupled to the memory banks, to implement an interleaving of memory addresses among the memory banks as a function of the number of banks actually present. Successive memory accesses are thus not unnecessarily delayed by the recovery times of the memory elements, and furthermore, any memory bank can be operationally removed from the system without physical disconnection. Delay elements (111,113,115) delay timing signals from the memory banks by an amount corresponding to the speed of the DRAM chips, so that chips of differing speeds can be used. <IMAGE></p> |
