Phase locked loop synchronizer for a resampling system having incompatible input and output sample rates.

摘要

The system converts input video signals in a studio format, such as CCIR 601 (625/25), into output video signals in another format, such as the Phase Alternate Line (PAL) format. The horizontal line scanning frequency of the input and output signals is the same. The signal conversion system uses an output clock signal to determine the relative timing of the input and output video signals. The signal is generated by a phase-locked loop which employs a crystal-controlled VCO. The phase of the signal produced by the VCO is adjusted to maintain the sampling clock signals of the input and output video signals in a set phase relationship. The phase error signal which is used to control the VCO is generated by comparing a first phase reference signal, generated from the output signal, to a second phase reference signal generated from the input signal. The output phase reference signal may be the synchronizing signal component of the converted video signal or an indication that a predetermined interpolation phase is being applied by the resampling system. The input phase reference signal may be the input clock signal or an indication of the start of a horizontal line interval.