发明名称 |
Data processor which efficiently accesses main memory and input/output devices |
摘要 |
A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.
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申请公布号 |
US5347636(A) |
申请公布日期 |
1994.09.13 |
申请号 |
US19920965534 |
申请日期 |
1992.10.23 |
申请人 |
NEC CORPORATION |
发明人 |
OOI, YASUSHI;MIKI, YOSHIYUKI |
分类号 |
G06F12/10;(IPC1-7):G06F15/00 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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