| 摘要 |
PURPOSE:To enable clock to be changed through the zone of 1 time slot and 2 time slot and generate a signal suitable for the production of test wave for high speed logic apparatus. CONSTITUTION:Input of a desired logic wave from the data terminal 11 is carried out and n spacings having different phases by one time slot from one another (n is integer more than 2) are formed by dividing by the data dividing FF 12a, 12b in accordance with the clock from the terminal 13. Preferable clock groups of the terminal 16, 26 are given to the clock dividing shift registers 27, 28 to divide the clock into n clocks in space having different phases by one time slot from one another. The outputs of this register 27, 28 and FF 12a, 12b are added to the control AND gate 31 to 34 and the clock signals divided in space by the space- divided logic data are controlled, the controlled clock signals are added to multiple OR gate 35, 36, and the outputs of the multipled signals are given to the output of the gate 35, 36 and then fed to the logic circuit. |
