| 摘要 |
PURPOSE:To decrease a code error rate by performing the clok-by-clock discriminative regeneration of a N-phase PSK modulated carrier by using its clocks and then by selecting either ''1'' or ''0'' appearing to be definite by a majority decision circuit. CONSTITUTION:A carrier clock signal, generated from a carrier by carrier clock signal generating circuit 10, is inputted to discriminative regenerating circuit 11. A two-phase PSK modulated carrier, on the other hand, is also inputted to circuit 11, where it is converted direct into a digital signal; on the basis of clocks of timing clock generating circuit 15, series-parallel converter circuit 12 converts it into the (m)-number parallel NRZ digital signals and majority-dicision logic circuit 13 decides on ''1'' (or ''0'') and outputs it. Consequently, the (m)-number values are extracted from the same time width and their majority decision is made, so that they can be extracted more accurately than conventional extraction of one value. |
