| 摘要 |
The frequency multiplier having a duty factor of 50% includes a first delayer for receiving a rectangular wave input signal having a duty factor of 50% and generating a delayed rectangular wave, a second delayer for receiving the rectangular wave input signal and generating a signal which is delayed by a quarter of a period of the output of the first delayer, and an exclusive OR gate for exclusively ORing the output of the first delayer with the output of the second delayer, thereby facilitating the integration of a circuit.
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