| 摘要 |
A memory cell array (10), which is one of a plurality of divisional memory cell arrays, is selected by use of an address signal (Ai). One of the word lines (WL) incorporated in the memory cell array (10) is selected by a row decoder (12). An OR circuit (17) is supplied with a control signal (BI) for setting a burn-in test mode, and with the address signal (Ai) for selecting the memory cell array (10). In the burn-in test mode, since the level of the control signal (BI) becomes high, the output level of the OR circuit (17) becomes high irrespective of the address signal (Ai). Thus, the overall memory cell arrays (10) are simultaneously selected, and hence more word lines (WL) than those accessed in a normal operation mode are simultaneously accessed. <IMAGE> |
