发明名称 Digital signal receiving apparatus with bit error controlled muting.
摘要 <p>A signal receiver that can function in any of three modes, such as normal mode, channel selecting mode, and mandatory announcement mode, is controlled by a microprocessor to mute the output signals or to release a muting operation depending upon the current mode. The signals being received contain an error detection/correction code and upon error decoding the number of error flags within predefined periods are checked to determine whether muting is required. The respective lengths of the predefined error flag checking periods are controlled in response to the current operating mode of the signal receiver. <IMAGE></p>
申请公布号 EP0614292(A1) 申请公布日期 1994.09.07
申请号 EP19940301400 申请日期 1994.02.28
申请人 SONY CORPORATION 发明人 HIRAYASU, MASATOSHI, C/O SONY CORPORATION
分类号 H04B1/10;H04B14/04;H04L1/00;(IPC1-7):H04H1/02;H04H1/00 主分类号 H04B1/10
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