| 摘要 |
<p>In a memory system including a memory cell array (305), a row decoder (301) and a column decoder (303), a first shift register (302) receives a first value outputted from said row decoder, to output a first shifted value obtained by shifting said first value, to said memory cell array for access to said memory cell array, and a second shift register (304) receiving a second value outputted from said column decoder, to output a second shifted value obtained by shifting said second value, to said memory cell array for access to said memory cell array. A shift control logic (414, 415) responds to advance of said program and an branch instruction for controlling the shift of said first and second shift registers. <IMAGE></p> |
