| 摘要 |
A parallel test circuit that can perform the parallel test and data reading of the memory device at the same time. By using it, one can shorten the test time. The parallel test circuit of the present invention has several MOS transistors N1 to NK where several data Data1 to DataK selected from the memory cell are input into each gate and their drains are commonly connected to an input/output line. Also, it has several MOS transistors n1 to nk where Data1 to &upbar& D which are complementary data of said Data1 to DataK are input into each gate and their drains are commonly connected to another input/output line. Finally, it has load transistors P1 and P2 used to pre-charge said input/output lines. During the normal reading operation, it switches on data line pairs that have been selected, and then reads their data. During the parallel test, it evaluates whether the data is erroneous according to the output voltage level of the input/output lines by inputting all the data at the same time. Since it can test all the data at the same time, the test time can be shortened. Also, unlike the conventional logic circuit, its circuit is less complicated.
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