发明名称 Master slice integrated circuit device
摘要 In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its associated power branch-off member and the respective power line.
申请公布号 US5345098(A) 申请公布日期 1994.09.06
申请号 US19920878527 申请日期 1992.05.05
申请人 SEIKO EPSON CORPORATION 发明人 HIRABAYASHI, YASUHISA;SAKUDA, TAKASHI;OKAWA, KAZUHIKO;OGUCHI, YASUHIRO
分类号 H01L21/82;H01L21/822;H01L23/528;H01L27/04;H01L27/118;(IPC1-7):H01L27/10;H01L27/15 主分类号 H01L21/82
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