发明名称 CODER FOR DIGITAL VIDEO SIGNAL
摘要 <p>PURPOSE:To utilize effectively a data transmission period by coding a digital video signal at a high compression rate and controlling adaptively bit allocation to two frame data when the data quantity of a coded output is made constant for each prescribed period. CONSTITUTION:The difference between an input frame P and a frame I generated by a local decoder is detected by a subtractor circuit 23, its absolute value is integrated for each block and an integrated output Ef is compared with two threshold levels Th1, Th2 at a comparator circuit 26. Data transmission of a block having a relation of Ef<=Th1 is omitted, and difference data of blocks having a relation of Th1<Ef<Th2 are subjected to DC transformation and processing of variable length coding. Blocks having the relation of Ef>=Th2 are subjected to in-frame coding processing. Since three modes are in existence as coding results of the frame P, the quantity of data generated from the frame P is fluctuated. Since the quantity of data generated from the frame P is less, data of excess blocks are added to data from the frame I and then bit allocation data T-B and B to the two frames are generated.</p>
申请公布号 JPH06245203(A) 申请公布日期 1994.09.02
申请号 JP19930051571 申请日期 1993.02.17
申请人 SONY CORP 发明人 YANAGIHARA HISAFUMI
分类号 H03M7/30;G06T9/00;H04N19/102;H04N19/107;H04N19/115;H04N19/126;H04N19/134;H04N19/137;H04N19/14;H04N19/142;H04N19/147;H04N19/149;H04N19/172;H04N19/176;H04N19/189;H04N19/196;H04N19/423;H04N19/46;H04N19/50;H04N19/503;H04N19/59;H04N19/60;H04N19/61;H04N19/625;H04N19/65;H04N19/70;H04N19/80;H04N19/85;H04N19/88;H04N19/91;H04N19/93;(IPC1-7):H04N7/133;G06F15/66 主分类号 H03M7/30
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