| 摘要 |
PURPOSE:To obtain a CODEC whose S/N is satisfactory in which a master clock signal is not necessary, and the frequency of a bit clock signal is not restricted. CONSTITUTION:When a synchronizing signal SB and a bit clock signal BC are supplied from an outside, a PLL circuit 120 is operated by using the signal SB as a reference signal, and the output signal is transmitted to a selecting circuit 140. Then, a frequency-division rate is set at a frequency dividing circuit 133 according to the output frequency of the signal BC, the signal BC is frequency-divided by the frequency-division rate, and transmitted to the selecting circuit 140. The selecting circuit 140 selects one of the output of the PLL circuit 120 and the output of the selecting circuit 140 according to the frequency of the signal BC, and outputs an inside clock signal $. Then, a clock signal or a control signal or the like to be used by SCF 101 and 201, A/D converter 102, and D/A converter 202 or the like are generated by control circuits 103 and 203 by the signal phi. |
