发明名称 4:2 adder and multiplier circuit employing the same.
摘要 <p>An adder (150) of four inputs and two outputs is a circuit for deriving CARRY and SUM satisfying in0 + in1 + in2 + in3 + cin = 2cout + 2CARRY + SUM, where in0, in1, in2, in3 are the first to fourth inputs, cin is the intermediate carry from the preceding digit and cout is the intermediaty carry to the next digit. Cout is calculated only from (in0,in1,in2,in3) and will not be influenced by cin. The adder (150) is to be employed in an intermediate sum generating circuit (310,320,...,400) of a multiplier. &lt;IMAGE&gt;</p>
申请公布号 EP0613082(A1) 申请公布日期 1994.08.31
申请号 EP19940102668 申请日期 1994.02.22
申请人 NEC CORPORATION 发明人 HAGIHARA, YASUHIKO, C/O NEC CORPORATION
分类号 G06F7/52;G06F7/509;G06F7/50;G06F7/53;G06F7/60;(IPC1-7):G06F7/60 主分类号 G06F7/52
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