| 摘要 |
The invention relates to a frequency divider consisting of N divide-by-2 circuits. According to the invention, the frequency divider comprises logic circuits making it possible to generate the end-of-frequency-division signal with the aid of the change in state of the most significant bit generated by the divide-by-2 circuit of order N. A binary code C representing an integer decimal value V is applied to the divider circuit. According to the invention, the frequency divider comprises circuits which make it possible to carry out variable-order division (V+1, V, ... V-p where p is a whole number greater than or equal to 1) for the same binary code C. |
