| 摘要 |
<p>A variable delay line (10) having a string of "slow" logic inverters (11) and an equal number of "fast" inverters (14) with inputs connected to corresponding "slow" inverter inputs. Transmission gates (15), coupling the "fast" inverter outputs to corresponding "slow" inverter outputs, vary the amount of coupling between the inverters. Maximum delay occurs with substantially no coupling between the "fast" and "slow" inverters and minimum delay occurs when maximum coupling occurs between the "fast" and "slow" inverters. The variable delay line may be configured into a variable frequency ring oscillator, useful in phase-locked-loops or the like. <IMAGE></p> |
