| 摘要 |
PURPOSE:To shorten the reading test times of many ROMs by reading data from plural ROMs in parallel, selecting each of the read data and outputting them onto an internal data bus. CONSTITUTION:The ROMs 1, 4 addressed by ROM address generation circuits 2, 5 are precharged, thereafter data in addresses O are read out simultaneously, and the data are held in ROM data read buffers 3 and 6. Next, by means of a ROM test address signal 14 from a ROM test address generation circuit 10, the buffers 3, 6 are alternately selected, so that ROM test read signals 13 are sequentially outputted from a ROM test read signal generation circuit 9. Subsequently, the data from the ROMs 1, 4 held in the buffers 3, 6 are sequentially held in a data bus buffer 11 through the internal bus 15 at the timing of its up edge in the order of the data in the address O of the ROMs 1, 4, and the data in the address 1 of the same 1, 4, ..., and the data are outputted to outside of the LSI. |
