发明名称 |
Leading one anticipator and floating point addition/subtraction apparatus |
摘要 |
A bit-discard amount anticipator anticipates a bit-discard amount within a one-bit error. A borrow propagator propagates a borrow from a least significant bit side. A selector modifies an output of the bit-discard amount anticipator to an accurate bit shift amount required at a normalization and outputs it, using information of the borrow propagator. The bit shift amount for the normalization in case where a bit discard is caused at a mantissa subtraction of a floating point calculation is accurately obtained, thus reducing a process at the normalization.
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申请公布号 |
US5343413(A) |
申请公布日期 |
1994.08.30 |
申请号 |
US19930084125 |
申请日期 |
1993.07.01 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
INOUE, GENICHIRO |
分类号 |
G06F5/01;G06F7/74;(IPC1-7):G06F7/00 |
主分类号 |
G06F5/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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