| 摘要 |
An error correction circuit wherein the coefficients of the error-location polynomial sigma (x) of any three-error correcting binary BCH code over the Galois Field GF(2m) are found from the first three odd components S1, S3, and S5 of the syndrome vector. The circuit traverses a binary decision tree to find the polynomial coefficients and can be realized totally with combinational logic. The correct equation for the final polynomial coefficients is found at the termination of the tree. The descent through this tree and the computation of the coefficients can be performed by parallel combinational logic. Addition over the Galois Field is performed in the standard representation with exclusive OR gates. Multiplication can be performed by converting the standard representation into a special representation that is passed through a pair of binary adders to form the product. Translation can then be made back to the standard representation. The coefficients of the error-location polynomial appear at the output of the circuit after a time representing the total combinational logic delay of the circuit from the time the syndrome vector is applied to the input.
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