发明名称 |
System and method for tolerating dynamic circuit decay |
摘要 |
The present invention tolerates the decay of a dynamic logic circuit by preserving the logic state of the output before the decay. A slow clock detector is configured to detect a slow clock condition of the clock pertaining to the dynamic logic circuit. A tolerant storage device is configured to preserve the data output by command of the slow clock detector upon a detection of the slow clock condition. |
申请公布号 |
US5343096(A) |
申请公布日期 |
1994.08.30 |
申请号 |
US19920885584 |
申请日期 |
1992.05.19 |
申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
HEIKES, CRAIG A.;MILLER, JR., ROBERT H. |
分类号 |
G11C11/409;G01R31/30;H03K19/003;H03K19/096;(IPC1-7):H03K19/003 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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