发明名称 METHOD OF INCREASING THE LAYOUT EFFICIENCY OF DIES ON A WAFER, AND INCREASING THE RATIO OF I/O AREA TO ACTIVE AREA PER DIE
摘要 Certain non-square dies, such as triangular dies (e.g. 202a, 202b,...), greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer (204) more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die (202a, 202b,...). <IMAGE>
申请公布号 EP0583625(A3) 申请公布日期 1994.08.24
申请号 EP19930111442 申请日期 1993.07.16
申请人 LSI LOGIC CORPORATION 发明人 ROSTOKER, MICHAEL D.
分类号 H01L21/02;G03F7/20;G06F17/50;H01L21/301;H01L21/822;H01L23/31;H01L23/485;H01L23/495;H01L27/02;H01L27/04;H01L29/06 主分类号 H01L21/02
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