发明名称 Testing circuit.
摘要 <p>A testing circuit is provided for testing the operability both of a load (30) and of a capacitor (26) incorporated into a main detonator circuit and arranged to discharge into the load for detonation thereof. A test pulse is generated at a central controller to which a ring of detonators is connected on a harness. The test pulse is routed via the harness for storage in the capacitor. A controlled switch (44) is operated to allow the capacitor to discharge into the load. A transistor (52) is operated by the discharge signal, the transistor having an output for delivering a discharge value signal (56) in response to the discharge signal remaining above or falling below a threshold value. The discharge value signal is latched and is in turn used to inhibit a local oscillator (66). The inhibited signal from the oscillator is routed back to the controller so as to indicate a fault either in the capacitor (26) or in the load (30). &lt;IMAGE&gt;</p>
申请公布号 EP0611944(A1) 申请公布日期 1994.08.24
申请号 EP19940301177 申请日期 1994.02.18
申请人 CSIR 发明人 MARSH, MICHAEL JOHN CAMILLE;HODSON, TREVOR MEREDITH;ATKINS, RAYMOND CATHERALL;TOLMAY, JAMES PIETER
分类号 F42C21/00;G01R31/02;(IPC1-7):F42C21/00 主分类号 F42C21/00
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