Double polysilicon EEPROM cell and corresponding manufacturing process.

摘要

A two-level polysilicon EEPROM memory cell, of a type which comprises a floating gate (12) transistor connected serially to a selection transistor (14) and having a further control gate (15) overlying the floating gate (12) with an intermediate dielectric layer (11) therebetween. A region (10) including a double implant (18,19) of the same dopant at two different concentrations is provided between the respective gate terminals of the selection transistor (14) and the memory cell (1). <IMAGE>