| 摘要 |
<p>In a digital filtering circuit for converting an input data signal (a) of a sampling frequency fs into an output data signal (OUT) of an oversampling frequency Nfs which is N times the sampling frequency fs. The digital filtering circuit comprises a combination of a calculating circuit (30), and first and second integrating circuits (40, 50). The first integrating circuit (40) integrates a calculated signal (d) in synchronism with the oversampling frequency Nfs to produce a first integration result signal (b) and a first delayed signal (e). The second integrating circuit (50) integrates the first delayed signal (e) in synchronism with the oversampling frequency Nfs to produce a second integration result signal (c) and a second delayed signal (f) as the output data signal (OUT). The calculating circuit (30) carries out a predetermined calculation on the input data signal (a), the first integration result signal (b), and the second integration result signal (c) in synchronism with the sampling frequency fs to produce the calculated signal (d). The predetermined calculation is represented by an equation as follows: d = {a - c - (1 + 3N)b/2}/N<2>. <IMAGE></p> |
