| 摘要 |
PURPOSE:To reduce the delay due to the skew of a main word line in a dynamic RAM using duplex word lines. CONSTITUTION:A driving circuit C2 for a word line selection power source activating signal line S1 is arranged at a peripheral part being on the prolonged line of main word decoder train. Then, a direction along which a signal outputting from the C2 and driving a word line selection power source line control circuit C3 flows in the S1 coincides with a direction along which a signal in a main word line MWL flows. Furthermore, the control circuits C3 are arranged with the same interval as the interval of word driver train WD, a word line selection power source driving circuit C4 controlled by the C3 is arranged at the edge of the word driver train WD, the thickness of the signal line S1 is adjusted and then, the delay is minimized since the wiring delaies of the main word line and signal line S1 coincide with each other. Besides, the wiring delaies of the main word line and a sense amplifier power source activating signal are made equal an a further high-speed operation is attained since driving circuits for the sense amplifier power source circuit activating signal are arranged at the cross points between sense amplifier array and main word decoder array. |
