| 摘要 |
PURPOSE:To correctly output data by providing a differentiating circuit, and outputting a signal obtained by allowing an output of a prescribed 4-input OR gate to be subjected to wave tail differentiation, as a reset signal. CONSTITUTION:When a reproducing clock exists in an AGC signal inputted from a demodulator, its signal becomes 'H'. Subsequently, when a clock 1 being a reproducing clock inputted from the outside is continued, an AGC signal 2 inputted from the outside becomes 'H'. Also, the clock 1 becomes an output 4 of a 2-input AND gate 3 without being masked by the signal 2 in the gate 3 and as for four outputs 6-9 of a first 4-bit register 5, only one becomes 'H' in order at every rise of the output of the gate 3. Next, the 4-input AND gate 5 executes an OR operation of a carry output of four pieces of (v)-ary counters. By the obtained timing, the 4-ary counter 20 controls four outputs of the register 5 and a multiplexer 27. Moreover, when an output subjected to wave tail differentiation by a differentiating circuit 18 is set as a reset signal, data can be outputted correctly. |
