发明名称 Semiconductor read only memory with paralleled selecting transistors for higher speed
摘要 A semiconductor ROM includes a plurality of word lines disposed in parallel and has a plurality of units which each includes: a first main bit line and a second main bit line which cross the word lines; first, second, third, and fourth, sub-bit lines disposed substantially in parallel to the first and second main bit lines, and each of which has a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns. First ends of the first sub-bit line and the third sub-bit line are connected to the first main bit line, and the second ends of the second sub-bit line and the fourth sub-bit line are connected to the second main bit line. First and second ones of the bank selecting switches are disposed in parallel between the first main bit line and the first sub-bit line, and third and fourth ones of the bank selecting switches are disposed in parallel between the second main bit line and the fourth sub-bit line. A fifth one of the bank selecting switches is disposed between the first main bit line and the third sub-bit line, and a sixth one of the bank selecting switches is disposed between the second main bit line and the second sub-bit line.
申请公布号 US5341337(A) 申请公布日期 1994.08.23
申请号 US19930121424 申请日期 1993.09.16
申请人 SHARP KABUSHIKI KAISHA 发明人 HOTTA, YASUHIRO
分类号 G11C7/18;G11C17/12;H01L21/8246;H01L27/112;(IPC1-7):G11C7/00 主分类号 G11C7/18
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